Datasheet RA2L2 (Renesas) - 3
| Fabricante | Renesas |
| Descripción | Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 128-KB code flash memory, 16-KB SRAM, USB 2.0 Full-Speed module (USBFS), USB Type-C® interface (USBCC), 12-bit A/D Converter, Security and Safety features. |
| Páginas / Página | 108 / 3 — Table 1.3. System (2 of 2). Feature. Functional description. Table 1.4. … |
| Formato / tamaño de archivo | PDF / 2.0 Mb |
| Idioma del documento | Inglés |
Table 1.3. System (2 of 2). Feature. Functional description. Table 1.4. Event link. Table 1.5. Direct memory access. Table 1.6
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Versión de texto del documento
RA2L2 Datasheet 1. Overview
Table 1.3 System (2 of 2) Feature Functional description
Clocks ● Main clock oscillator (MOSC) ● Sub-clock oscillator (SOSC) ● High-speed on-chip oscillator (HOCO) ● Middle-speed on-chip oscillator (MOCO) ● Low-speed on-chip oscillator (LOCO) ● IWDT-dedicated on-chip oscillator ● Clock out support Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to Measurement Circuit (CAC) be measured (measurement target clock) within the time generated by the clock selected as the measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also controls non-maskable interrupts. Key Interrupt Function (KINT) The key interrupt function (KINT) generates the key interrupt by detecting rising or falling edge on the key interrupt input pins. Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. Register write protection The register write protection function protects important registers from being overwritten due to software errors. The registers to be protected are set with the Protect Register (PRCR). Memory Protection Unit (MPU) The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow interrupt or watchdog timer reset. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value in the registers.
Table 1.4 Event link Feature Functional description
Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention.
Table 1.5 Direct memory access Feature Functional description
Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request.
Table 1.6 Timers (1 of 2) Feature Functional description
General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 1 channel and a 16-bit timer with GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. Port Output Enable for GPT (POEG) The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins in the output disable state R01DS0445EJ0110 Rev.1.10 Page 3 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice
Table 1.3 System (2 of 2) Feature Functional description
Clocks ● Main clock oscillator (MOSC) ● Sub-clock oscillator (SOSC) ● High-speed on-chip oscillator (HOCO) ● Middle-speed on-chip oscillator (MOCO) ● Low-speed on-chip oscillator (LOCO) ● IWDT-dedicated on-chip oscillator ● Clock out support Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to Measurement Circuit (CAC) be measured (measurement target clock) within the time generated by the clock selected as the measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also controls non-maskable interrupts. Key Interrupt Function (KINT) The key interrupt function (KINT) generates the key interrupt by detecting rising or falling edge on the key interrupt input pins. Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. Register write protection The register write protection function protects important registers from being overwritten due to software errors. The registers to be protected are set with the Protect Register (PRCR). Memory Protection Unit (MPU) The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow interrupt or watchdog timer reset. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value in the registers.
Table 1.4 Event link Feature Functional description
Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention.
Table 1.5 Direct memory access Feature Functional description
Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request.
Table 1.6 Timers (1 of 2) Feature Functional description
General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 1 channel and a 16-bit timer with GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. Port Output Enable for GPT (POEG) The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins in the output disable state R01DS0445EJ0110 Rev.1.10 Page 3 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice