Datasheet RA2L2 (Renesas) - 6
| Fabricante | Renesas |
| Descripción | Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 128-KB code flash memory, 16-KB SRAM, USB 2.0 Full-Speed module (USBFS), USB Type-C® interface (USBCC), 12-bit A/D Converter, Security and Safety features. |
| Páginas / Página | 108 / 6 — Figure 1.1. Block diagram |
| Formato / tamaño de archivo | PDF / 2.0 Mb |
| Idioma del documento | Inglés |
Figure 1.1. Block diagram
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Versión de texto del documento
link to page 6 link to page 7 link to page 8 RA2L2 Datasheet 1. Overview 1.2 Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memory Bus Arm Cortex-M23 System 128 KB code flash MPU MPU POR/LVD Clocks MOSC/SOSC 4 KB data flash Reset NVIC (H/M/L) OCO 16 KB SRAM Mode control System timer Power control DMA DTC Test and DBG Interface ICU CAC Register write KINT protection Timers Communication interfaces GPT32 × 1 GPT16 × 6 SCI × 4 SSIE × 1 I3C × 1 AGTW × 2 UARTA × 2 SPI × 1 USBFS × 1 RTC CAN × 1 USBCC × 1 WDT/IWDT Event link Data processing Analogs ELC CRC ADC12 TSN Security DOC TRNG Note: Not available on all parts
Figure 1.1 Block diagram
1.3 Part Numbering Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a list of products. R01DS0445EJ0110 Rev.1.10 Page 6 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice
Figure 1.1 Block diagram
1.3 Part Numbering Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a list of products. R01DS0445EJ0110 Rev.1.10 Page 6 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice