Datasheet SN74HCS05 (Texas Instruments) - 7
| Fabricante | Texas Instruments |
| Descripción | 6-ch, 2-V to 6-V inverters with Schmitt-Trigger inputs and open-drain outputs |
| Páginas / Página | 24 / 7 — SN74HCS05. www.ti.com. 7 Parameter Measurement Information. Figure 7-1. … |
| Formato / tamaño de archivo | PDF / 1.0 Mb |
| Idioma del documento | Inglés |
SN74HCS05. www.ti.com. 7 Parameter Measurement Information. Figure 7-1. Load Circuit
Línea de modelo para esta hoja de datos
Versión de texto del documento
SN74HCS05 www.ti.com
SCLS797A – JUNE 2020 – REVISED OCTOBER 2020
7 Parameter Measurement Information
• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. • The outputs are measured one at a time, with one input transition per measurement. VCC Test VCC 90% 90% Point Input S 10% 10% 1 0 V (1) (1) R tr t L From Output f Under Test VOH C (1) 90% 90% L Output 10% 10% VOL (1) (1) A. C tr tf L= 50 pF and includes probe and jig capacitance.
Figure 7-1. Load Circuit Figure 7-2. Voltage Waveforms Transition Times
VCC Input 50% 50% 0 V t (1) (2) PLZ tPZL VOH Output 50% 10% VCC VOL t (2) (1) PZL tPLZ VOH Output 50% 10% VOL A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74HCS05 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions Pin Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Switching Characteristics 6.7 Operating Characteristics 6.8 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Open-Drain CMOS Outputs 8.3.2 CMOS Schmitt-Trigger Inputs 8.3.3 Clamp Diode Structure 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.1.1 Power Considerations 9.2.1.2 Input Considerations 9.2.1.3 Output Considerations 9.2.2 Detailed Design Procedure 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation 12.2 Related Links 12.3 Support Resources 12.4 Trademarks 12.5 Electrostatic Discharge Caution 12.6 Glossary 13 Mechanical, Packaging, and Orderable Information
SCLS797A – JUNE 2020 – REVISED OCTOBER 2020
7 Parameter Measurement Information
• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. • The outputs are measured one at a time, with one input transition per measurement. VCC Test VCC 90% 90% Point Input S 10% 10% 1 0 V (1) (1) R tr t L From Output f Under Test VOH C (1) 90% 90% L Output 10% 10% VOL (1) (1) A. C tr tf L= 50 pF and includes probe and jig capacitance.
Figure 7-1. Load Circuit Figure 7-2. Voltage Waveforms Transition Times
VCC Input 50% 50% 0 V t (1) (2) PLZ tPZL VOH Output 50% 10% VCC VOL t (2) (1) PZL tPLZ VOH Output 50% 10% VOL A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74HCS05 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions Pin Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Switching Characteristics 6.7 Operating Characteristics 6.8 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Open-Drain CMOS Outputs 8.3.2 CMOS Schmitt-Trigger Inputs 8.3.3 Clamp Diode Structure 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.1.1 Power Considerations 9.2.1.2 Input Considerations 9.2.1.3 Output Considerations 9.2.2 Detailed Design Procedure 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation 12.2 Related Links 12.3 Support Resources 12.4 Trademarks 12.5 Electrostatic Discharge Caution 12.6 Glossary 13 Mechanical, Packaging, and Orderable Information