Datasheet SN74HCS05 (Texas Instruments) - 8

FabricanteTexas Instruments
Descripción6-ch, 2-V to 6-V inverters with Schmitt-Trigger inputs and open-drain outputs
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SN74HCS05. www.ti.com. 8 Detailed Description 8.1 Overview. 8.2 Functional Block Diagram

SN74HCS05 www.ti.com 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram

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SN74HCS05
SCLS797A – JUNE 2020 – REVISED OCTOBER 2020
www.ti.com 8 Detailed Description 8.1 Overview
This device contains six independent inverter with open-drain outputs and Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic.
8.2 Functional Block Diagram
One of Six Channels xA xY
8.3 Feature Description 8.3.1 Open-Drain CMOS Outputs
This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. When placed into the high-impedance state, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10 kΩ resistor can be used to meet these requirements. Unused open-drain CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔV T in the Electrical Characteristics, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: SN74HCS05 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions Pin Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Switching Characteristics 6.7 Operating Characteristics 6.8 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Open-Drain CMOS Outputs 8.3.2 CMOS Schmitt-Trigger Inputs 8.3.3 Clamp Diode Structure 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.1.1 Power Considerations 9.2.1.2 Input Considerations 9.2.1.3 Output Considerations 9.2.2 Detailed Design Procedure 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation 12.2 Related Links 12.3 Support Resources 12.4 Trademarks 12.5 Electrostatic Discharge Caution 12.6 Glossary 13 Mechanical, Packaging, and Orderable Information