Datasheet MAX6951 (Analog Devices) - 3

Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951 ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Slow Segment Blink Period Eight digits scanned, OSC = RC oscillator, fS LOWBLIN K 1 s (Internal Oscillator) RSET = 56kΩ, CSET = 27pF Fast Segment Blink Period Eight digits scanned, OSC = RC oscillator, fFASTBLIN K 0.5 s (Internal Oscillator) RSET = 56kΩ, CSET = 27pF Fast or Slow Segment Blink Duty 49.9 50 50.1 % Cycle (Note 2) Digit Drive Sink Current IDIGIT TA = +25°C, VLED = 2.4V 240 320 400 mA Segment Drive Source Current ISEG TA = +25°C, VLED = 2.4V -30 -40 -50 mA Digit Drive Sink Current (Note 2) IDIGIT TA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V 80 mA Segment Drive Source Current ISEG TA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V -10 mA (Note 2) Slew Rate Rise Time ∆ISEG/∆t TA = +25°C 35 mA/µs
LOGIC INPUTS
Input Current DIN, CLK, CS IIH, IIL VIN = 0 or V+ -2 2 µA Logic High Input Voltage DIN, VIH 2.4 V CLK, CS Logic Low Input Voltage DIN, VIL 0.4 V CLK, CS H yster esi s V ol tag e D IN , C LK, C S ∆VI 0.5 V
TIMING CHARACTERISTICS
(Figure 1) CLK Clock Period tCP 38.4 ns CLK Pulse Width High tCH 19 ns CLK Pulse Width Low tCL 19 ns C S Fall to CLK Ri se S etup Ti m e tCSS 9.5 ns CLK Ri se to CS Rise Hold Time tCSH 3 ns DIN Setup Time tDS 9.5 ns DIN Hold Time tDH 0 ns CS Pulse High tCSW 19 ns
TIMING CHARACTERISTICS (V+ = +2.7V)
(Note 2) CLK Clock Period tCP 50 ns CLK Pulse Width High tCH 24 ns CLK Pulse Width Low tCL 24 ns C S Fall to CLK Ri se Setup Time tCSS 12 ns CLK Ri se to CS Rise Hold Time tCSH 4 ns DIN Setup Time tDS 12 ns DIN Hold Time tDH 4 ns CS Pulse High tCSW 24 ns
Note 1:
All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
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