Datasheet MAX6951 (Analog Devices) - 10

Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers Table 5. Configuration Register Format REGISTER DATA MODE ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Configuration register 0x04 X X R T E B 0 S
Table 6. Shutdown Control (S Data Bit D0) Format REGISTER DATA MODE ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Shutdown 0x04 X X R T E B 0 0 Normal operation 0x04 X X R T E B 0 1
Table 7. Blink Rate Selection (B Data Bit D2) Format REGISTER DATA MODE ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 MAX6950/MAX6951
S l ow - b l i nki ng seg m ents b l i nk on for 1s, off for 1s 0x04 X X R T E 0 0 S w i th fOS C = 4M H z Fast-blinking segments blink on for 0.5s, off for 0x04 X X R T E 1 0 S 0.5s with fOSC = 4MHz
Table 8. Global Blink Enable/Disable (E Data Bit D3) Format REGISTER DATA MODE ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Blink function is 0x04 X X R T 0 B 0 S disabled Blink function is 0x04 X X R T 1 B 0 S enabled
Table 9. Global Blink Timing Synchronization (T Data Bit D4) Format REGISTER DATA MODE ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Blink timing counters 0x04 X X R 0 E B 0 S are unaffected Blink timing counters are cleared on the 0x04 X X R 1 E B 0 S rising edge of CS Each LED digit is represented by 2 bytes of memory, 1 registers are mapped so that a digit’s data can be byte in plane P0 and the other in plane P1. Each LED updated in plane P0, or plane P1, or both planes at the digit’s segment is represented by 2 bits of memory, 1 same time (Table 3). bit from the appropriate byte in each plane. The digit
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