Datasheet TPD7110F (Toshiba) - 3

TPD7110F
6. Pin Description Table 6.1 Pin Description No. Name I/O Pin Description
1 IN INPUT Gate driver input pin 2 N.C. - No-connect pin 3 GND - GND pin 4 SUB - Keep this pin open to activate reverse connection protection of the power supply 5 SENSE INPUT Reverse current sense pin 6 SOURCE INPUT Source connection pin for external N-channel MOSFET 7 GATE OUTPUT Gate drive pin for external N-channel MOSFET 8 VDD - Power supply pin
7. Operation Description
This product controls the on/off state of an N-channel MOSFET (hereafter referred to as "MOSFET") used in circuits such as ideal diodes or back-to-back relay switch configurations. When the MOSFET is on, if reverse current is detected from the load side, the MOSFET is turned off to block the reverse current. Additionally, the MOSFET is turned off when the power supply voltage drops, becomes excessively high, or is connected in reverse.
7.1. Normal On/Off Operation
When the IN pin is in a high state (i.e., at or above the high-level input voltage, VIH), the charge pump operates and generates a high-level output voltage between the GATE and SOURCE pins to turn on the MOSFET. Depending on the power supply voltage (VDD), either VGS(1) or VGS(3) is output as the high-level gate-source voltage. When the IN pin is in a low state (i.e., at or below the low-level input voltage, VIL), the charge pump stops, the off-driver turns on, and the voltage between the GATE and SOURCE pins becomes a low level (VGSL), turning off the MOSFET.Stopping the charge pump during the MOSFET off state helps reduce current consumption. The rise time of the output voltage when the power supply voltage is 12 V is defined by tON1 and tON2, and the fall time is defined by tOFF1. V IH VIN VIL VGS(3) 10V 6V VGS 1.5V VGSL tON1 tOFF1 tON2
Fig. 7.1 Normal On/Off Waveform (VDD = 12 V)
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