Datasheet SR6P3EC4 (STMicroelectronics)

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SR6P3EC4 SR6P3EC6
Data brief Stellar SR6 P3E line—32-bit Arm® Cortex®‑R52+ automotive integration MCU 4× Cortex®‑R52+ cores, 19.5 MB xMemory, 1.8 MB RAM, with embedded virtualization, safety, and security
Features
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Highlights
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Cores and accelerators
• 4 × 32-bit Cortex®‑R52+ cores (2 in split-lock configuration): – Configurable as either 4 cores (2 of them in lockstep configuration) or 3 cores (all of them in lockstep configuration) – Arm® v8-R compliant – Single precision floating-point unit (FPU) – New privilege level for real-time virtualization
Product summary
– Up to 500 MHz
Part number Package
• 1 Cortex®‑M4 multipurpose accelerator running at up to 200 MHz, in lockstep SR6P3EC4 FPBGA292 configuration SR6P3EC6 FPBGA476 • 4 eDMA engines
Neural processing unit
• Neural ART Accelerator™ 11 • Energy efficient NPU capable of accelerating a wide range of neural network models
Memories
• xMemory: up to 19.5 MB extensible on-chip nonvolatile memory (NVM) depending on ordered part number: – PCM (phase-change memory) as nonvolatile memory – Up to 19 MB code NVM, with A/B swap OTA mechanism (up to 2× 9.5 MB) – 512 KB HSM-dedicated code NVM • 384 KB data NVM (256 KB + 128 KB dedicated to HSM) • Up to 1792 KB on-chip general-purpose SRAM
DB5468
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Rev 4
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February 2026
www.st.com For further information, contact your local STMicroelectronics sales office. Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN