Datasheet CH32X033, CH32X035 (Nanjing Qinheng Microelectronics) - 7

CH32X035 Datasheet https://wch-ic.com
1.4.5 Power Supply Monitor
A power-on reset (POR)/power-down reset (PDR) circuit is integrated inside the chip, which is always active to ensure that the system operates when the power supply exceeds 2V; when VDD is below the set threshold (VPOR/PDR), it puts the device in reset without the need to use external reset circuitry. In addition, the system has a programmable voltage monitor (PVD), which needs to be turned on by software, to compare the voltage magnitude of the VDD supply with the set threshold VPVD. Turning on the corresponding edge interrupt of the PVD allows you to receive an interrupt notification when VDD falls to the PVD threshold or rises to the PVD threshold. Refer to Chapter 3 for VPOR/PDR and VPVD values.
1.4.6 System Voltage Regulator LDO
After resetting, the system voltage regulator is automatically switched on. There are two modes of operation depending on the application mode. On mode: normal running operation, providing stable core power. Low-power mode: low-power operation of the regulator when the CPU is in Standby mode.
1.4.7 Low-power Mode
The system supports three low-power modes, which can be selected to achieve the best balance for conditions such as low-power consumption, short start-up times and multiple wake-up events. Sleep mode In Sleep mode, only the CPU clock is stopped, but all peripheral clocks are powered normally and the peripherals are in working condition. This mode is the shallowest low-power mode, but the fastest wake-up can be achieved. Exit condition: any interrupt or wake-up event. Stop mode This mode puts the FLASH into low-power mode and the RC oscillator of the HSI is switched off. Exit conditions: any external interrupt/event (EXTI signal), external reset signal on RST, IWDG reset, where EXTI signal includes one of the 24 external I/O ports, output of PVD, wake-up signal of USB, wake-up signal of USB PD, etc. Standby mode This mode FLASH enters low-power mode, the RC oscillator of HSI is switched off and the system LDO enters low-power mode. Exit conditions: any external interrupt/event (EXTI signal), external reset signal on RST, IWDG reset, where the EXTI signal includes one of the 24 external I/O ports, the output of PVD, the wake-up signal of USB, the wake-up signal of USB PD, etc.
1.4.8 Programmable Fast Interrupt Controller (PFIC)
The chip has a built-in Programmable Fast Interrupt Controller (PFIC) that supports up to 255 interrupt vectors, providing flexible interrupt management with minimal interrupt latency. Currently the chip manages 7 core private interrupts and 39 peripheral interrupt management, with other interrupt sources reserved. the PFIC registers are all accessible in both user and machine privileged modes. 2 individually maskable interrupts Provide one non-maskable interrupt NMI Support Hardware Prologue/Epilogue (HPE) without instruction overhead Provide 4 Vector Table Free (VTF) for faster access to interrupt service routines V2.3 5 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules