Preliminary Datasheet EPC2103 (Efficient Power Conversion) - 2

EPC2103 – Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet STATIC CHARACTERISTICS Parameter Conditions Q1 Control FET Q2 Sync FET
Q1: V Maximum Drain – Source Voltage (BV GS = 0 V, ID = 430 µA DSS) 80 V Q2: VGS = 0 V, ID = 430 µA Maximum Drain – Source Leakage VDS = 64 V, VGS = 0 V 325 µA 325 µA Maximum RDS(on) VGS = 5 V, ID = 20 A 5.5 mΩ 5.5 mΩ Typical RDS(on) VGS = 5 V, ID = 20 A 3.8 mΩ 3.8 mΩ Q1: I Gate – Source Threshold Voltage D = 7 mA, VDS = VGS 0.8 V < VGS(TH) < 2.5 V Q2: ID = 7 mA, VDS = VGS Gate – Source Maximum Positive Leakage VGS = 5 V 6.5 mA 6.5 mA Gate – Source Maximum Negative Leakage VGS = -4 V -325 µA -325 µA TJ = 25 °C unless otherwise stated
DYNAMIC CHARACTERISTICS Typical Value Parameter Conditions Q1 Control FET Q2 Sync FET Unit
C 0.76 0.76 ISS (Input Capacitance) C 0.46 0.63 OSS (Output Capacitance) V nF DS = 40 V, VGS = 0 V CRSS (Reverse Transfer Capacitance) 0.0087 0.0087 QG (Total Gate Charge) VDS = 40 V, ID = 20 A, VGS = 5 V 6.5 6.5 Q 2 2 GS (Gate to Source Charge) Q 1.3 1.3 GD (Gate to Drain Charge) VDS = 40 V, ID = 20 A nC QG(TH) (Gate Charge at Threshold) 1.5 1.5 QOSS (Output Charge) VDS = 40 V, VGS = 0 V 29 39 QRR (Source-Drain Recovery Charge) 0 0 TJ = 25 °C unless otherwise stated

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