Datasheet ADF4602 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Single-Chip, Multiband 3G Femtocell Transceiver |
| Páginas / Página | 36 / 8 — ADF4602. TIMING CHARACTERISTICS. Table 2. Parameter Limit. TMIN to TMAX … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 662 Kb |
| Idioma del documento | Inglés |
ADF4602. TIMING CHARACTERISTICS. Table 2. Parameter Limit. TMIN to TMAX Unit. Test. Conditions/Comments. WRITE. t5 t6. SCLK. t3 t4. SDATA
Línea de modelo para esta hoja de datos
Versión de texto del documento
ADF4602 TIMING CHARACTERISTICS
VDD = 3.1 V to 3.6 V, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 2. Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 62 ns min SEN high to write time t2 10 ns min SEN to SCLK setup time t3 10 ns min SDATA to SCLK setup time t4 10 ns min SDATA to SCLK hold time t5 31 ns min SCLK high duration t6 31 ns min SCLK low duration t7 10 ns min SEN to SCLK hold time t8 20 ns max SEN to SDATA valid delay t9 20 ns max SCLK to SDATA valid delay t10 20 ns max SEN to SDATA disabled delay
WRITE t5 t6 SCLK t3 t4 SDATA W[25] W[24] W[1] W[0] t2 t7
2
SEN t
00
1
2- 09 07 Figure 2. Serial Interface Write Diagram
READ REQUEST READ SCLK t9 SDATA Q[25] Q[24] Q[1] Q[0] R[25] R[24] R[1] R[0] t10 SEN t8 3
3 o
OR
r m
M
ore
ORE
sele
A
c
D
t
F
ed d
460
e
2
vice SY
SC
S
L
C
K
LK
PE
pe
RI
r
O
io
D
d
S
s dr
DRI
iv
V
es
ES
R
S
SDA
DAT
TA
A
3 DBB releases 00
HOST RELEASES
2-
S
RSD
DAT
A
A
TA 09 07 Figure 3. Serial Interface Read/Write Diagram Rev. A | Page 8 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION TRANSMITTER DESCRIPTION I/Q Baseband I/Q Modulator VCO Output TX Output Baluns DACS GENERAL PURPOSE OUTPUTS RECEIVER DESCRIPTION LNAs Mixers Baseband Section Gain Control DC Offset Compensation POWER MANAGEMENT FREQUENCY SYNTHESIS Reference Path SERIAL PORT INTERFACE (SPI) Format OPERATION AND TIMING Read REGISTERS REGISTER MAP REGISTER DESCRIPTION SOFTWARE INITIALIZATION PROCEDURE INITIALIZATION SEQUENCE Nonvolatile Memory (NVM) Initialization Programming Transmit and Receive frequencies APPLICATIONS INFORMATION INTERFACING THE ADF4602 TO THE AD9963 AD9963 ADC Inputs Interfacing to the AD9963 Rx Baseband Inputs AD9963 DAC Outputs Reference Voltage Current Scaling Resistor, RSET Gain Scaling Parameters RECEIVE SENSITIVITY Interfacing to the AD9963 TX Baseband Outputs OUTLINE DIMENSIONS ORDERING GUIDE
VDD = 3.1 V to 3.6 V, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 2. Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 62 ns min SEN high to write time t2 10 ns min SEN to SCLK setup time t3 10 ns min SDATA to SCLK setup time t4 10 ns min SDATA to SCLK hold time t5 31 ns min SCLK high duration t6 31 ns min SCLK low duration t7 10 ns min SEN to SCLK hold time t8 20 ns max SEN to SDATA valid delay t9 20 ns max SCLK to SDATA valid delay t10 20 ns max SEN to SDATA disabled delay
WRITE t5 t6 SCLK t3 t4 SDATA W[25] W[24] W[1] W[0] t2 t7
2
SEN t
00
1
2- 09 07 Figure 2. Serial Interface Write Diagram
READ REQUEST READ SCLK t9 SDATA Q[25] Q[24] Q[1] Q[0] R[25] R[24] R[1] R[0] t10 SEN t8 3
3 o
OR
r m
M
ore
ORE
sele
A
c
D
t
F
ed d
460
e
2
vice SY
SC
S
L
C
K
LK
PE
pe
RI
r
O
io
D
d
S
s dr
DRI
iv
V
es
ES
R
S
SDA
DAT
TA
A
3 DBB releases 00
HOST RELEASES
2-
S
RSD
DAT
A
A
TA 09 07 Figure 3. Serial Interface Read/Write Diagram Rev. A | Page 8 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION TRANSMITTER DESCRIPTION I/Q Baseband I/Q Modulator VCO Output TX Output Baluns DACS GENERAL PURPOSE OUTPUTS RECEIVER DESCRIPTION LNAs Mixers Baseband Section Gain Control DC Offset Compensation POWER MANAGEMENT FREQUENCY SYNTHESIS Reference Path SERIAL PORT INTERFACE (SPI) Format OPERATION AND TIMING Read REGISTERS REGISTER MAP REGISTER DESCRIPTION SOFTWARE INITIALIZATION PROCEDURE INITIALIZATION SEQUENCE Nonvolatile Memory (NVM) Initialization Programming Transmit and Receive frequencies APPLICATIONS INFORMATION INTERFACING THE ADF4602 TO THE AD9963 AD9963 ADC Inputs Interfacing to the AD9963 Rx Baseband Inputs AD9963 DAC Outputs Reference Voltage Current Scaling Resistor, RSET Gain Scaling Parameters RECEIVE SENSITIVITY Interfacing to the AD9963 TX Baseband Outputs OUTLINE DIMENSIONS ORDERING GUIDE