Datasheet Si5351 (Silicon Labs) - 5

FabricanteSilicon Labs
DescripciónI2C-Programmable Any-Frequency CMOS Clock Generator + VCXO
Páginas / Página41 / 5 — S i 5 3 5 1 A / B / C - B. 1. Electrical Specifications. Table 2. …
Formato / tamaño de archivoPDF / 1.8 Mb
Idioma del documentoInglés

S i 5 3 5 1 A / B / C - B. 1. Electrical Specifications. Table 2. Recommended Operating Conditions. Parameter. Symbol

S i 5 3 5 1 A / B / C - B 1 Electrical Specifications Table 2 Recommended Operating Conditions Parameter Symbol

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Si5351

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S i 5 3 5 1 A / B / C - B 1. Electrical Specifications Table 2. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA –40 25 85 °C 3.0 3.3 3.60 V Core Supply Voltage VDD 2.25 2.5 2.75 V 1.71 1.8 1.89 V Output Buffer Voltage VDDOx 2.25 2.5 2.75 V 3.0 3.3 3.60 V
Notes:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same time as VDD.
Table 3. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Enabled 3 outputs — 22 35 mA Core Supply Current IDD Enabled 8 outputs — 27 45 mA Output Buffer Supply Current I (Per Output)* DDOx CL = 5 pF — 2.2 5.6 mA CLKIN, SDA, SCL ICLKIN — — 10 µA Input Current Vin < 3.6 V IVC VC — — 30 µA 3.3 V VDDO, default high Output Impedance ZO — 50 — drive
*Note:
Output clocks less than or equal to 100 MHz.
Rev. 1.0 5
Document Outline 1. Electrical Specifications 2. Detailed Block Diagrams 3. Functional Description 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) 3.1.2. External Clock Input (CLKIN) 3.1.3. Voltage Control Input (VC) 3.2. Synthesis Stages 3.3. Output Stage 3.4. Spread Spectrum 3.5. Control Pins (OEB, SSEN) 3.5.1. Output Enable (OEB) 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only 4. I2C Interface 5. Configuring the Si5351 5.1. Writing a Custom Configuration to RAM 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs 5.5. Replacing Crystals, Crystal Oscillators, and PLLs 5.6. Applying a Reference Clock at XTAL Input 5.7. HCSL Compatible Outputs 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.5. Unused Pins 6.6. Trace Characteristics 7. Register Map Summary 8. Register Descriptions 9. Si5351 Pin Descriptions 9.1. Si5351A 20-pin QFN 9.2. Si5351B 20-Pin QFN 9.3. Si5351C 20-Pin QFN 9.4. Si5351A 10-Pin MSOP 10. Ordering Information 11. Package Outlines 11.1. 20-pin QFN 12. Land Pattern: 20-Pin QFN 12.1. 10-Pin MSOP Package Outline 13. Land Pattern: 10-Pin MSOP 14. Top Marking 14.1. 20-Pin QFN Top Marking 14.2. Top Marking Explanation 14.3. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Document Change List