Datasheet Si5351 (Silicon Labs) - 6

S i 5 3 5 1 A / B / C - B Table 4. AC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
From VDD = VDDmin to valid Power-up Time TRDY output clock, CL = 5 pF, — 2 10 ms fCLKn > 1 MHz From V Power-up Time, PLL Bypass DD = VDDmin to valid T output clock, C — 0.5 1 ms Mode BYP L = 5 pF, fCLKn > 1 MHz From OEB pulled low to valid Output Enable Time TOE clock output, CL = 5 pF, — — 10 µs fCLKn > 1 MHz Output Frequency Transition T Time FREQ fCLKn > 1 MHz — — 10 µs Output Phase Offset PSTEP — 333 — ps/step Down spread. Selectable in 0.1% –0.1 — –2.5 % Spread Spectrum Frequency steps. SS Deviation DEV Center spread. Selectable in ±0.1 — ±1.5 % 0.1% steps. Spread Spectrum Modulation SS Rate MOD 30 31.5 33 kHz
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range Vc 0 VDD/2 VDD V VCXO Gain (configurable) Kv Vc = 10–90% of VDD, VDD = 3.3 V 18 — 150 ppm/V VCXO Control Voltage Linearity KVL Vc = 10–90% of VDD –5 — +5 % VCXO Pull Range PR V (configurable) DD = 3.3 V* ±30 0 ±240 ppm VCXO Modulation Bandwidth — 10 — kHz
*Note:
Contact Silicon Labs for 2.5 V VCXO operation.
Table 5. Input Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Crystal Frequency fXTAL 25 — 27 MHz CLKIN Input Low Voltage VIL –0.1 — 0.3 x VDD V CLKIN Input High Voltage VIH 0.7 x VDD — 3.60 V CLKIN Frequency Range fCLKIN 10 — 100 MHz
6 Rev. 1.0
Document Outline 1. Electrical Specifications 2. Detailed Block Diagrams 3. Functional Description 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) 3.1.2. External Clock Input (CLKIN) 3.1.3. Voltage Control Input (VC) 3.2. Synthesis Stages 3.3. Output Stage 3.4. Spread Spectrum 3.5. Control Pins (OEB, SSEN) 3.5.1. Output Enable (OEB) 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only 4. I2C Interface 5. Configuring the Si5351 5.1. Writing a Custom Configuration to RAM 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs 5.5. Replacing Crystals, Crystal Oscillators, and PLLs 5.6. Applying a Reference Clock at XTAL Input 5.7. HCSL Compatible Outputs 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.5. Unused Pins 6.6. Trace Characteristics 7. Register Map Summary 8. Register Descriptions 9. Si5351 Pin Descriptions 9.1. Si5351A 20-pin QFN 9.2. Si5351B 20-Pin QFN 9.3. Si5351C 20-Pin QFN 9.4. Si5351A 10-Pin MSOP 10. Ordering Information 11. Package Outlines 11.1. 20-pin QFN 12. Land Pattern: 20-Pin QFN 12.1. 10-Pin MSOP Package Outline 13. Land Pattern: 10-Pin MSOP 14. Top Marking 14.1. 20-Pin QFN Top Marking 14.2. Top Marking Explanation 14.3. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Document Change List