Datasheet CH9121 (Nanjing Qinheng Microelectronics) - 3
| Fabricante | Nanjing Qinheng Microelectronics |
| Descripción | Network serial port transparent transmission chip |
| Páginas / Página | 15 / 3 — 4. Pin Definitions |
| Revisión | V2.5 |
| Formato / tamaño de archivo | PDF / 283 Kb |
| Idioma del documento | Inglés |
4. Pin Definitions
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CH9121 Datasheet https://wch-ic.com
4. Pin Definitions
Table 4-1 CH9121T Pin definitions CH9121T Pin name Type Pin description Pin No. 1 TXP Differential output in 10BASE-T/100BASE-TX MDI mode; I/O 2 TXN Differential input in 10BASE-T/100BASE-TX MDIX mode. 19 RXP Differential input in 10BASE-T/100BASE-TX MDI mode; I/O 20 RXN Differential output in 10BASE-T/100BASE-TX MDIX mode. 3 VDDK P Place an external 1uF ground capacitor close to the chip. For 3.3V main power input, it is recommended to place a 0.1uF 18 VCC33 P capacitor in parallel with a 10uF or 4.7uF capacitor close to the chip. For the power input of the I/O interface, it is recommended to 8 VCCIO P place a 0.1uF ground capacitor close to the chip. 17 GND P Common ground terminal. Crystal oscillator input, requires an external 25MHz crystal, or 4 XI I external clock input, with built-in crystal matching capacitor. Crystal oscillator inverts and needs to be connected to the other 5 XO O end of an external 25MHz crystal. It has a built-in crystal matching capacitor. Alternate pin, built-in pull-up resistor, detect pin level during power-on. Low level selects RESET function, floating or high level selects LINK function. LINK network connection indicator LED output: Low level indicates that the Ethernet PHY is connected; 6 LINK/RESET I/O,PU High level indicates that the Ethernet PHY is not connected. RESET control input (restore factory settings): If the detection pin is at a low level for 2 seconds during power- on, CH9121 will be restored to factory settings. After the pin returns to a high level, the LINK function will be enabled. Carrier sensing indicator LED output: 7 ACT O LED flashes to indicate carrier sensing signal. 9 TXD2 O Serial port 2 data output. 10 RXD2 I,PU Serial port 2 data input, built-in pull-up resistor. Serial port configuration mode setting pin, built-in pull-up resistor, when a low level is detected, it enters the serial port 11 CFG I,PU configuration mode, and exits the configuration mode when it is left floating or at a high level. Transmit status output, used to control the RS485 transmitting 12 TNOW2 O and receiving switching of serial port 2. 13 RXD1 I,PU Serial port 1 data input, built-in pull-up resistor. 14 TXD1 O Serial port 1 data output. 15 CTS I,PD Clear transmit Input: V2.5 3 Document Outline 1. Overview 2. Features 3. Pinouts 4. Pin Definitions 5. Function Parameter Descriptions 5.1 Overview 5.2 Basic Parameters 5.3 Port Parameter 5.4 Default Configuration 6. Function Descriptions 6.1 UART 6.1.1 Serial Baud Rate 6.2 Other Hardware 7. Parameters 7.1 Absolute Maximum Value 7.2 Electrical Parameters 7.3 Power Consumption 7.4 AC Electrical Characteristics and Timing 8. Package Information 8.1 TSSOP20 8.2 LQFP64M 9. Applications 9.1 CH9121T Reference Circuit 9.2 CH9121A Reference Circuit
4. Pin Definitions
Table 4-1 CH9121T Pin definitions CH9121T Pin name Type Pin description Pin No. 1 TXP Differential output in 10BASE-T/100BASE-TX MDI mode; I/O 2 TXN Differential input in 10BASE-T/100BASE-TX MDIX mode. 19 RXP Differential input in 10BASE-T/100BASE-TX MDI mode; I/O 20 RXN Differential output in 10BASE-T/100BASE-TX MDIX mode. 3 VDDK P Place an external 1uF ground capacitor close to the chip. For 3.3V main power input, it is recommended to place a 0.1uF 18 VCC33 P capacitor in parallel with a 10uF or 4.7uF capacitor close to the chip. For the power input of the I/O interface, it is recommended to 8 VCCIO P place a 0.1uF ground capacitor close to the chip. 17 GND P Common ground terminal. Crystal oscillator input, requires an external 25MHz crystal, or 4 XI I external clock input, with built-in crystal matching capacitor. Crystal oscillator inverts and needs to be connected to the other 5 XO O end of an external 25MHz crystal. It has a built-in crystal matching capacitor. Alternate pin, built-in pull-up resistor, detect pin level during power-on. Low level selects RESET function, floating or high level selects LINK function. LINK network connection indicator LED output: Low level indicates that the Ethernet PHY is connected; 6 LINK/RESET I/O,PU High level indicates that the Ethernet PHY is not connected. RESET control input (restore factory settings): If the detection pin is at a low level for 2 seconds during power- on, CH9121 will be restored to factory settings. After the pin returns to a high level, the LINK function will be enabled. Carrier sensing indicator LED output: 7 ACT O LED flashes to indicate carrier sensing signal. 9 TXD2 O Serial port 2 data output. 10 RXD2 I,PU Serial port 2 data input, built-in pull-up resistor. Serial port configuration mode setting pin, built-in pull-up resistor, when a low level is detected, it enters the serial port 11 CFG I,PU configuration mode, and exits the configuration mode when it is left floating or at a high level. Transmit status output, used to control the RS485 transmitting 12 TNOW2 O and receiving switching of serial port 2. 13 RXD1 I,PU Serial port 1 data input, built-in pull-up resistor. 14 TXD1 O Serial port 1 data output. 15 CTS I,PD Clear transmit Input: V2.5 3 Document Outline 1. Overview 2. Features 3. Pinouts 4. Pin Definitions 5. Function Parameter Descriptions 5.1 Overview 5.2 Basic Parameters 5.3 Port Parameter 5.4 Default Configuration 6. Function Descriptions 6.1 UART 6.1.1 Serial Baud Rate 6.2 Other Hardware 7. Parameters 7.1 Absolute Maximum Value 7.2 Electrical Parameters 7.3 Power Consumption 7.4 AC Electrical Characteristics and Timing 8. Package Information 8.1 TSSOP20 8.2 LQFP64M 9. Applications 9.1 CH9121T Reference Circuit 9.2 CH9121A Reference Circuit