Datasheet CH9121 (Nanjing Qinheng Microelectronics) - 4

CH9121 Datasheet https://wch-ic.com If it is a high level, serial port 1 blocks the next data transmission when the current data transmission ends, and can be connected to the peer RTS to implement hardware flow control. Alternate pin with built-in pull-up resistor to detect pin level during power-on. An external pull-down resistor of about 4K7 makes this pin low during power-on and selects the TNOW1 function. If it is left floating or high during power-on, the RTS function is selected. RTS transmit request output: 16 RTS/TNOW1 I/O,PU If it is a low level, it means that serial port 1 is ready to receive data and can be connected to the other end's CTS to implement hardware flow control. TNOW1 output: Transmitting status output, used to control the RS485 transmitting and receiving switching of serial port 1. Table 4-2 CH9121A Pin definitions CH9121A Pin name Type Pin description Pin No. 4 RXP Differential input in 10BASE-T/100BASE-TX MDI mode; I/O 5 RXN Differential output in 10BASE-T/100BASE-TX MDIX mode. 7 TXP Differential output in 10BASE-T/100BASE-TX MDI mode; I/O 8 TXN Differential input in 10BASE-T/100BASE-TX MDIX mode. 3.3V power supply input, it is recommended that 0.1uF parallel 2/12 VCC33 P 10uF or 4.7uF ground capacitor be placed close to the chip. 19 VDDK P Place an external 1uF ground capacitor close to the chip. 28/43 VDDK P Place an external 0.1uF ground capacitor close to the chip. For the power input of the I/O interface, it is recommended to 21/29/40/45/63 VCCIO P place a 0.1uF ground capacitor close to the chip. 3/9/13/18/20/37/41/44 GND P Common ground terminal. 1/6/14/15/16/17/22/23/ 24/25/26/27/34/35/38/3 NC - Reserved, leave it suspended. 9/42/47/48/49/50/54/61 /62/64 Crystal oscillator input, requires an external 25MHz crystal, or 10 XI I external clock input, with built-in crystal matching capacitor. The crystal oscillator inverts and needs to be connected to the 11 XO O other end of an external 25MHz crystal. It has a built-in crystal matching capacitor. In TCP mode, port 1 connection status indication output, low 30 TCPCS1 O level is valid. 31 RUN O CH9121 operation status indication output. Network configuration enable pin, built-in pull-up resistor, 32 CFGEN I,PU detects pin level when powered on, if it is low level when V2.5 4 Document Outline 1. Overview 2. Features 3. Pinouts 4. Pin Definitions 5. Function Parameter Descriptions 5.1 Overview 5.2 Basic Parameters 5.3 Port Parameter 5.4 Default Configuration 6. Function Descriptions 6.1 UART 6.1.1 Serial Baud Rate 6.2 Other Hardware 7. Parameters 7.1 Absolute Maximum Value 7.2 Electrical Parameters 7.3 Power Consumption 7.4 AC Electrical Characteristics and Timing 8. Package Information 8.1 TSSOP20 8.2 LQFP64M 9. Applications 9.1 CH9121T Reference Circuit 9.2 CH9121A Reference Circuit