Datasheet NV6257 (Navitas Semiconductor) - 9
| Fabricante | Navitas Semiconductor |
| Descripción | 650V Half-Bridge GaNFast Power IC |
| Páginas / Página | 20 / 9 — NV6257. Functional Description. Start-Up. Fig. 5 |
| Formato / tamaño de archivo | PDF / 734 Kb |
| Idioma del documento | Inglés |
NV6257. Functional Description. Start-Up. Fig. 5
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NV6257 Functional Description
This GaN Power IC includes many functions designed for proper half-bridge operation during different circuit operating modes. The following functional description contains additional information regarding the IC operating modes and pin functionality.
Start-Up
Integrated into the design are UVLO circuits for disabling the IC when V , V and V are below their CC DDL B respective UVLO+ thresholds. During UVLO Mode, the gate drive and half-bridge power FETs are disabled and V consumes a low current. At start-up when the V supply voltage increases (Fig 5), the voltages at CC CC the V pin and the DZ pin both increase as well. The V supply voltage will exceed the V threshold DDL L DDL DDUV+ (4.8V typical) and then get limited by the internal regulator to the voltage level set by the Zener diode at the DZ pin (6.2 V, typical). The Zener diodes at the DZ and DZ pins should be a low-current type with a flat L L H Zener voltage curve (above the knee) in the sub-100 µA current range (see Table I for recommended Zener diode part numbers). The V voltage continues to increase until it exceeds the VCC threshold (9.25V CC UV+ typical) and the IC enters Normal Operating Mode. Initially, only the low-side half-bridge FET will turn on with the IN PWM input signal. The high-side supply V charges up through the internal bootstrap FET during the L B IN on-time. When V exceeds the VB threshold (9.25V typical), the high-side circuitry will be enabled and L B UV+ the high-side FET will turn on with the next IN PWM input signal. H
Fig. 5
. Start-up timing diagram Revised 8-1-18 Navitas Semiconductor Confidential Page 9
NV6257 Functional Description
This GaN Power IC includes many functions designed for proper half-bridge operation during different circuit operating modes. The following functional description contains additional information regarding the IC operating modes and pin functionality.
Start-Up
Integrated into the design are UVLO circuits for disabling the IC when V , V and V are below their CC DDL B respective UVLO+ thresholds. During UVLO Mode, the gate drive and half-bridge power FETs are disabled and V consumes a low current. At start-up when the V supply voltage increases (Fig 5), the voltages at CC CC the V pin and the DZ pin both increase as well. The V supply voltage will exceed the V threshold DDL L DDL DDUV+ (4.8V typical) and then get limited by the internal regulator to the voltage level set by the Zener diode at the DZ pin (6.2 V, typical). The Zener diodes at the DZ and DZ pins should be a low-current type with a flat L L H Zener voltage curve (above the knee) in the sub-100 µA current range (see Table I for recommended Zener diode part numbers). The V voltage continues to increase until it exceeds the VCC threshold (9.25V CC UV+ typical) and the IC enters Normal Operating Mode. Initially, only the low-side half-bridge FET will turn on with the IN PWM input signal. The high-side supply V charges up through the internal bootstrap FET during the L B IN on-time. When V exceeds the VB threshold (9.25V typical), the high-side circuitry will be enabled and L B UV+ the high-side FET will turn on with the next IN PWM input signal. H
Fig. 5
. Start-up timing diagram Revised 8-1-18 Navitas Semiconductor Confidential Page 9