Datasheet NV6257 (Navitas Semiconductor) - 10
| Fabricante | Navitas Semiconductor |
| Descripción | 650V Half-Bridge GaNFast Power IC |
| Páginas / Página | 20 / 10 — NV6257. Functional Description (cont.). Normal Operating Mode. Fig. 6 |
| Formato / tamaño de archivo | PDF / 734 Kb |
| Idioma del documento | Inglés |
NV6257. Functional Description (cont.). Normal Operating Mode. Fig. 6
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NV6257 Functional Description (cont.) Normal Operating Mode
During normal operating mode, the EN pin is above the V threshold (4V maximum), V is being regulated EN+ CC at a sufficient level (15 V typical) by the auxiliary power supply of the power converter, and V is at a sufficient B level (as set by V and the internal bootstrap circuit). The PWM input signals at the IN and IN pins turn the CC L H gates of the internal high- and low-side power FETs on and off at the desired duty-cycle, frequency and dead- time. The input logic signal at the IN pin turns the low-side half-bridge power FET on and off (0=OFF, 1=ON), L and the input logic signal at the IN pin turns the high-side half-bridge power FET on and off (0=OFF, 1=ON). H As the PWM inputs are turned on and off in a complementary manner each switching cycle, the V pin (half- SW bridge mid-point) is then switched between P (IN =1, IN =0) and V (IN =0, IN =1) at the given frequency GND L H IN L H and duty-cycle (Fig. 6). This Power GaN IC includes shoot-through protection circuitry that prevents both power FETs from turning on simultaneously. The IC also includes an internal bootstrap FET for supplying the high-side circuitry. The bootstrap FET is enabled during normal operating mode and is turned on each PWM switching cycle only when the IN pin is ‘HIGH” and the low-side power FET is on. This will allow the V capacitor to be L B charged up each switching cycle for properly maintaining the necessary high-side supply voltage. The VB capacitor value should be sized correctly such that the V voltage is maintained at a sufficient level above B UVLO- during normal operation. Should the V -V voltage decrease below the falling VB UVLO threshold B SW UV- (8.75V typical) at any time, then the high-side power FET will turn off and become disabled until V -V B SW increases again above the VB threshold (9.25V typical). UV+
Fig. 6
. PWM inputs and V output voltage timing diagram during normal ZVS operation SW Revised 8-1-18 Navitas Semiconductor Confidential Page 10
NV6257 Functional Description (cont.) Normal Operating Mode
During normal operating mode, the EN pin is above the V threshold (4V maximum), V is being regulated EN+ CC at a sufficient level (15 V typical) by the auxiliary power supply of the power converter, and V is at a sufficient B level (as set by V and the internal bootstrap circuit). The PWM input signals at the IN and IN pins turn the CC L H gates of the internal high- and low-side power FETs on and off at the desired duty-cycle, frequency and dead- time. The input logic signal at the IN pin turns the low-side half-bridge power FET on and off (0=OFF, 1=ON), L and the input logic signal at the IN pin turns the high-side half-bridge power FET on and off (0=OFF, 1=ON). H As the PWM inputs are turned on and off in a complementary manner each switching cycle, the V pin (half- SW bridge mid-point) is then switched between P (IN =1, IN =0) and V (IN =0, IN =1) at the given frequency GND L H IN L H and duty-cycle (Fig. 6). This Power GaN IC includes shoot-through protection circuitry that prevents both power FETs from turning on simultaneously. The IC also includes an internal bootstrap FET for supplying the high-side circuitry. The bootstrap FET is enabled during normal operating mode and is turned on each PWM switching cycle only when the IN pin is ‘HIGH” and the low-side power FET is on. This will allow the V capacitor to be L B charged up each switching cycle for properly maintaining the necessary high-side supply voltage. The VB capacitor value should be sized correctly such that the V voltage is maintained at a sufficient level above B UVLO- during normal operation. Should the V -V voltage decrease below the falling VB UVLO threshold B SW UV- (8.75V typical) at any time, then the high-side power FET will turn off and become disabled until V -V B SW increases again above the VB threshold (9.25V typical). UV+
Fig. 6
. PWM inputs and V output voltage timing diagram during normal ZVS operation SW Revised 8-1-18 Navitas Semiconductor Confidential Page 10